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60 mhz 2000 v/s monolithic op amp ad844 rev. f information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?1989C2009 analog devices, inc. all rights reserved. features wide bandwidth 60 mhz at gain of ?1 33 mhz at gain of ?10 slew rate: 2000 v/s 20 mhz full power bandwidth, 20 v p-p, r l = 500 fast settling: 100 ns to 0.1% (10 v step) differential gain error: 0.03% at 4.4 mhz differential phase error: 0.16 at 4.4 mhz low offset voltage: 150 v maximum (b grade) low quiescent current: 6.5 ma available in tape and reel in accordance with eia-481-a standard applications flash adc input amplifiers high speed current dac interfaces video buffers and cable drivers pulse amplifiers functional block diagrams null 1 ?in 2 +in 3 ?v s 4 null 8 +v s 7 output 6 tz 5 ad844 top view (not to scale) 00897-001 figure 1. 8-lead pdip (n) and 8-lead cerdip (q) packages nc offsetnull ?in nc +in nc v? nc nc offsetnull v+ nc output tz nc nc 1 2 3 4 16 15 14 13 5 12 6 11 7 10 8 9 nc = no connect ad844 top view (not to scale) 00897-002 figure 2. 16-lead soic (r) package general description the ad844 is a high speed monolithic operational amplifier fabricated using the analog devices, inc., junction isolated complementary bipolar (cb) process. it combines high band- width and very fast large signal response with excellent dc performance. although optimized for use in current-to-voltage applications and as an inverting mode amplifier, it is also suitable for use in many noninverting applications. the ad844 can be used in place of traditional op amps, but its current feedback architecture results in much better ac perfor- mance, high linearity, and an exceptionally clean pulse response. this type of op amp provides a closed-loop bandwidth that is determined primarily by the feedback resistor and is almost independent of the closed-loop gain. the ad844 is free from the slew rate limitations inherent in traditional op amps and other current-feedback op amps. peak output rate of change can be over 2000 v/s for a full 20 v output step. settling time is typically 100 ns to 0.1%, and essentially independent of gain. the ad844 can drive 50 loads to 2.5 v with low distortion and is short-circuit protected to 80 ma. the ad844 is available in four performance grades and three package options. in the 16-lead soic (rw) package, the ad844j is specified for the commercial temperature range of 0c to 70c. the ad844a and ad844b are specified for the industrial temperature range of ?40c to +85c and are available in the cerdip (q) package. the ad844a is also available in an 8-lead pdip (n). the ad844s is specified over the military temperature range of ?55c to +125c. it is available in the 8-lead cerdip (q) package. a and s grade chips and devices processed to mil-std-883b, rev. c are also available. product highlights 1. the ad844 is a versatile, low cost component providing an excellent combination of ac and dc performance. 2. it is essentially free from slew rate limitations. rise and fall times are essentially independent of output level. 3. the ad844 can be operated from 4.5 v to 18 v power supplies and is capable of driving loads down to 50 , as well as driving very large capacitive loads using an external network. 4. the offset voltage and input bias currents of the ad844 are laser trimmed to minimize dc errors; v os drift is typically 1 v/c and bias current drift is typically 9 na/c. 5. the ad844 exhibits excellent differential gain and differential phase characteristics, making it suitable for a variety of video applications with bandwidths up to 60 mhz. 6. the ad844 combines low distortion, low noise, and low drift with wide bandwidth, making it outstanding as an input amplifier for flash analog-to-digital converters (adcs).
ad844 rev. f | page 2 of 20 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? functional block diagrams ............................................................. 1 ? general description ......................................................................... 1 ? product highlights ........................................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? absolute maximum ratings ............................................................ 5 ? metallization photograph ............................................................ 5 ? esd caution .................................................................................. 5 ? typical performance characteristics ............................................. 6 ? inverting gain-of-1 ac characteristics .................................... 8 ? inverting gain-of-10 ac characteristics .................................. 9 ? inverting gain-of-10 pulse response ...................................... 10 ? noninverting gain-of-10 ac characteristics ........................ 11 ? understanding the ad844 ............................................................ 12 ? open-loop behavior ................................................................. 12 ? response as an inverting amplifier ......................................... 12 ? response as an i-v converter .................................................. 13 ? circuit description of the ad844 ............................................ 13 ? response as a noninverting amplifier .................................... 14 ? noninverting gain of 100 ......................................................... 14 ? using the ad844 ............................................................................ 15 ? board layout ............................................................................... 15 ? input impedance ........................................................................ 15 ? driving large capacitive loads ............................................... 15 ? settling time ............................................................................... 15 ? dc error calculation ................................................................ 16 ? noise ............................................................................................ 16 ? video cable driver using 5 v supplies ................................ 16 ? high speed dac buffer ............................................................ 17 ? 20 mhz variable gain amplifier ............................................. 17 ? outline dimensions ....................................................................... 19 ? ordering guide .......................................................................... 20 ? revision history 2/09rev. e to rev f updated format .................................................................. universal changes to features section............................................................ 1 changes to differential phase error parameter, table 1 ............. 3 changes to figure 13 ........................................................................ 8 changes to figure 18 ........................................................................ 9 changes to figure 23 and figure 24 ............................................. 11 changes to figure 42 and high speed dac buffer section ..... 17 updated outline dimensions ....................................................... 19 changes to ordering guide .......................................................... 20 1/03 data sheet changed from rev. d to rev. e. updated features ............................................................................... 1 edit to tpc 18 ................................................................................... 7 edits to figure 13 and figure 14 ................................................... 13 updated outline dimensions ....................................................... 15 11/01 data sheet changed from rev. c to rev. d. edits to specifications ...................................................................... 2 edits to absolute maximum ratings .............................................. 3 edits to ordering guide ................................................................... 3
ad844 rev. f | page 3 of 20 specifications t a = 25c and v s = 15 v dc, unless otherwise noted. table 1. ad844j/ad844a ad844b ad844s parameter conditions min typ max min typ max min typ max unit input offset voltage 1 50 300 50 150 50 300 v t min to t max 75 500 75 200 125 500 v vs. temperature 1 1 5 1 5 v/c vs. supply 5 v to 18 v initial 4 20 4 10 4 20 v/v t min to t max 4 4 10 4 20 v/v vs. common mode v cm = 10 v initial 10 35 10 20 10 35 v/v t min to t max 10 10 20 10 35 v/v input bias current negative input bias current 1 200 450 150 250 200 450 na t min to t max 800 1500 750 1100 1900 2500 na vs. temperature 9 9 15 20 30 na/c vs. supply 5 v to 18 v initial 175 250 175 200 175 250 na/v t min to t max 220 220 240 220 300 na/v vs. common mode v cm = 10 v initial 90 160 90 110 90 160 na/v t min to t max 110 110 150 120 200 na/v positive input bias current 1 150 400 100 200 100 400 na t min to t max 350 700 300 500 800 1300 na vs. temperature 3 3 7 7 15 na/c vs. supply 5 v to 18 v initial 80 150 80 100 80 150 na/v t min to t max 100 100 120 120 200 na/v vs. common mode v cm = 10 v initial 90 150 90 120 90 150 na/v t min to t max 130 130 190 140 200 na/v input characteristics input resistance negative input 50 65 50 65 50 65 positive input 7 10 7 10 7 10 m input capacitance negative input 2 2 2 pf positive input 2 2 2 pf input common-mode voltage range 10 10 10 v input voltage noise f 1 khz 2 2 2 nv/hz input current noise negative input f 1 khz 10 10 10 pv/hz positive input f 1 khz 12 12 12 pv/hz open-loop transresistance v out = 10 v r l = 500 2.2 3.0 2.8 3.0 2.2 3.0 m t min to t max 1.3 2.0 1.6 2.0 1.3 1.6 m transcapacitance 4.5 4.5 4.5 pf differential gain error 2 f = 4.4 mhz 0.03 0.03 0.03 % differential phase error 2 f = 4.4 mhz 0.16 0.16 0.16 degree
ad844 rev. f | page 4 of 20 ad844j/ad844a ad844b ad844s parameter conditions min typ max min typ max min typ max unit frequency response small signal bandwidth 3 , 4 gain = ?1 60 60 60 mhz gain = ?10 33 33 33 mhz total harmonic distortion f = 100 khz, 2 v rms 5 0.005 0.005 0.005 % settling time 10 v output step 15 v supplies gain = ?1, to 0.1% 5 100 100 100 ns gain = ?10, to 0.1% 6 100 100 100 ns 2 v output step 5 v supplies gain = ?1, to 0.1% 5 110 110 110 ns gain = ?10, to 0.1% 6 100 100 100 ns output slew rate overdriven input 1200 2000 1200 2000 1200 2000 v/s full power bandwidth thd = 3% v out = 20 v p-p 5 v s = 15 v 20 20 20 mhz v out = 2 v p-p 5 v s = 5 v 20 20 20 mhz output characteristics voltage r l = 500 10 11 10 11 10 11 v short-circuit current 80 80 80 ma t min to t max 60 60 60 ma output resistance open loop 15 15 15 power supply operating range 4.5 18 4.5 18 4.5 18 v quiescent current 6.5 7.5 6.5 7.5 6.5 7.5 ma t min to t max 7.5 8.5 7.5 8.5 7.5 8.5 ma 1 rated performance after a 5 minute warm-up at t a = 25c. 2 input signal 285 mv p-p carrier (40 ire) ri ding on 0 mv to 642 mv (90 ire) ramp. r l = 100 ; r1, r2 = 300 . 3 for gain = ?1, input signal = 0 dbm, c l = 10 pf, r l = 500 , r1 = 500 , and r2 = 500 in . figure 29 figure 29 figure 29 figure 29. 4 for gain = ?10, input signal = 0 dbm, c l =10 pf, r l = 500 , r1 = 500 , and r2 = 50 in . 5 c l = 10 pf, r l = 500 , r1 = 1 k, r2 = 1 k in . 6 c l = 10 pf, r l = 500 , r1 = 500 , r2 = 50 in
ad844 rev. f | page 5 of 20 absolute maximum ratings table 2. parameter ratings supply voltage 18 v power dissipation 1 1.1 w output short-circuit duration indefinite input common-mode voltage v s differential input voltage 6 v inverting input current continuous 5 ma transient 10 ma storage temperature range (q) ?65 c to +150 c storage temperature range (n, rw) ?65 c to +125 c lead temperature (soldering, 60 sec) 300 c esd rating 1000 v 1 28-lead pdip package: ja = 90c/w. 8-lead cerdip package: ja = 110c/w. 16-lead soic package: ja = 100c/w. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. metallization photograph contact factory for latest dimensions. dimensions shown in inches and (millimeters). ? in null null + v s 0.076 (1.9) +in ?v s substrate connected to +v s tz output 0.095 (2.4) 00897-003 figure 3. die photograph esd caution
ad844 rev. f | page 6 of 20 typical performance characteristics t a = 25c and v s = 15 v, unless otherwise noted. 70 60 50 40 30 supply voltage (v) ?3db bandwidth (mhz) 20 0 5 10 15 00897-004 figure 4. ?3 db bandwidth vs. supply voltage, r1 = r2 = 500 ?60 ?70 100 1k 10k 100k ?80 ?90 ?100 ?110 ?120 ?130 input frequency (hz) harmonic distortion (db) third harmonic second harmonic 1v rms 00897-005 figure 5. harmonic distortion vs. input frequency, r1 = r2 = 1 k ?50 0 50 100 150 5 4 3 2 1 0 temperature (c) transresistance (m ? ) r l = r l = 500 ? r l = 50 ? 00897-006 figure 6. transresistance vs. temperature 20 15 0 10 5 supply voltage (v) input voltage (v) 20 0 5 10 15 t a = 25c 00897-007 figure 7. noninverting input vo ltage swing vs. supply voltage 20 15 0 10 5 supply voltage (v) output voltage (v) 20 0 5 10 15 r l = 500 ? t a = 25c 00897-008 figure 8. output voltage swing vs. supply voltage temperature (-c) supply current (ma) 10 140 ?60 ?40 ?20 0 20 40 60 80 100 120 9 8 7 6 5 4 v s = 5v v s = 15v 00897-009 figure 9. quiescent supply current vs. temperature and supply voltage
ad844 rev. f | page 7 of 20 ?50 0 50 100 150 2 1 0 ?1 ?2 temperature (c) input bias current (a) i bn i bp 00897-010 figure 10. inverting input bias current (i bn ) and noninverting input bias current (i bp ) vs. temperature 10k 100k 1m 10m 100m 100 10 1 0.1 0.01 frequency (hz) output impedance ( ? ) 5v supplies 00897-011 figure 11. output impedance vs. freq uency, gain = ?1, r1 = r2 = 1 k temperature (-c) ?3db bandwidth (mhz) 140 ?60 ?40 ?20 0 20 40 60 80 100 120 40 35 30 25 20 15 10 v s = 5v v s = 15v 0 0897-012 figure 12. C3 db bandwidth vs. temper ature, gain = ?1, r1 = r2 = 1 k
ad844 rev. f | page 8 of 20 inverting gain-of-1 ac characteristics r2 ad844 + ? r1 + v s 4.7 ? 4.7 ? 0.22 f 0.22 f output c l r l ?in ?v s 00897-013 figure 13. inverting amplifier, gain of ?1 (r1 = r2) 6 ?24 0 ?6 ?12 ?18 100m 1m 100k 10m frequency (hz) gain (db) r1 = r2 = 500 ? r1 = r2 = 1k ? 00897-014 figure 14. gain vs. frequency for gain = ?1, r l = 500 , c l = 0 pf ? 180 50 0 25 ?210 ?240 ?270 ?300 ?330 r1 = r2 = 500 ? r1 = r2 = 1k ? frequency (mhz) phase (degrees) 00897-015 figure 15. phase vs. frequency for gain = ?1, r l = 500 , c l = 0 pf 0 0897-016 5v 10 20ns 100 0 90 figure 16. large signal pulse response, gain = ?1, r1 = r2 = 1 k 0 0897-017 10 20ns 100 0 500nv 90 figure 17. small signal pulse response, gain = ?1, r1 = r2 = 1 k
ad844 rev. f | page 9 of 20 inverting gain-of-10 ac characteristics 50 ? ad844 + ? 500 ? + v s 4.7 ? 4.7 ? 0.22 f 0.22 f output c l r l ?in ?v s 00897-018 figure 18. gain of ?10 amplifier 100m 1m 100k 10m 26 ?4 20 14 8 2 frequency (hz) gain (db) r l = 500 ? r l = 50 ? 00897-019 figure 19. gain vs. frequency, gain = ?10 ? 180 50 0 25 ?210 ?240 ?270 ?300 ?330 frequency (mhz) phase (degrees) r l = 500 ? r l = 50 ? 00897-020 figure 20. phase vs. frequency, gain = ?10
ad844 rev. f | page 10 of 20 inverting gain-of-10 pulse response 0 0897-021 5v 10 20ns 100 0 90 figure 21. large signal pulse response, gain = C10, r l = 500 0 0897-022 10 20ns 100 0 500nv 90 figure 22. small signal pulse response, gain = ?10, r l = 500
ad844 rev. f | page 11 of 20 noninverting gain-of-10 ac characteristics +v s ?v s 0.22f 0.22f output r l ?in 4.7 ? 4.7 ? 450? 50? + ? ad844 c l 00897-023 figure 23. noninverting gain of +10 amplifier 100m 1m 100k 10m 26 ?4 20 14 8 2 frequency (hz) gain (db) r l = 500 ? r l = 50 ? 00897-024 figure 24. gain vs. frequency, gain = +10 ? 180 50 0 25 ?210 ?240 ?270 ?300 ?330 frequency (mhz) phase (degrees) r l = 500 ? r l = 50 ? 00897-025 figure 25. phase vs. frequency, gain = +10 00897-026 2v 10 100 90 0 100ns figure 26. noninverting amplifier large signal pulse response, gain = +10, r l = 500 00897-027 10 100 90 0 200nv 50ns figure 27. small signal pulse response, gain = +10, r l = 500
ad844 rev. f | page 12 of 20 understanding the ad844 the ad844 can be used in ways similar to a conventional op amp while providing performance advantages in wideband applications. however, there are important differences in the internal structure that need to be understood to optimize the performance of the ad844 op amp. open-loop behavior figure 28 shows a current feedback amplifier reduced to essen- tials. sources of fixed dc errors, such as the inverting node bias current and the offset voltage, are excluded from this model. the most important parameter limiting the dc gain is the transresistance, r t , which is ideally infinite. a finite value of r t is analogous to the finite open-loop voltage gain in a conven- tional op amp. the current applied to the inverting input node is replicated by the current conveyor to flow in resistor r t . the voltage developed across r t is buffered by the unity gain voltage follower. voltage gain is the ratio r t /r in . with typical values of r t = 3 m and r in = 50 , the voltage gain is about 60,000. the open-loop current gain, another measure of gain that is determined by the beta product of the transistors in the voltage follower stage (see figure 31 ), is typically 40,000. +1 +1 i in r in i in r t c t 00897-028 figure 28. equivalent schematic the important parameters defining ac behavior are the transcapacitance, c t , and the external feedback resistor (not shown). the time constant formed by these components is analogous to the dominant pole of a conventional op amp and thus cannot be reduced below a critical value if the closed-loop system is to be stable. in practice, c t is held to as low a value as possible (typically 4.5 pf) so that the feedback resistor can be maximized while maintaining a fast response. the finite r in also affects the closed-loop response in some applications. the open-loop ac gain is also best understood in terms of the transimpedance rather than as an open-loop voltage gain. the open-loop pole is formed by r t in parallel with c t . because c t is typically 4.5 pf, the open-loop corner frequency occurs at about 12 khz. however, this parameter is of little value in determining the closed-loop response. response as an inverting amplifier figure 29 shows the connections for an inverting amplifier. unlike a conventional amplifier, the transient response and the small signal bandwidth are determined primarily by the value of the external feedback resistor, r1, rather than by the ratio of r1/r2 as is customarily the case in an op amp application. this is a direct result of the low impedance at the inverting input. as with conventional op amps, th e closed-loop gain is ?r1/r2. the closed-loop transresistance is the parallel sum of r1 and r t . because r1 is generally in the range of 500 to 2 k and r t is about 3 m, the closed-loop transresistance is only 0.02% to 0.07% lower than r1. this small error is often less than the resistor tolerance. when r1 is fairly large (above 5 k) but still much less than r t , the closed-loop hf response is dominated by the time constant r1 c t . under such conditions, the ad844 is overdamped and provides only a fraction of its bandwidth potential. because of the absence of slew rate limitations under these conditions, the circuit exhibits a simple single-pole response even under large signal conditions. in figure 29 , r3 is used to properly terminate the input if desired. r3 in parallel with r2 gives the terminated resistance. as r1 is lowered, the signal bandwidth increases, but the time constant r1 c t becomes comparable to higher order poles in the closed- loop response. therefore, the closed-loop response becomes complex, and the pulse response shows overshoot. when r2 is much larger than the input resistance, r in , at pin 2, most of the feedback current in r1 is delivered to this input, but as r2 becomes comparable to r in , less of the feedback is absorbed at pin 2, resulting in a more heavily damped response. consequently, for low values of r2, it is possible to lower r1 without causing instability in the closed-loop response. table 3 lists combinations of r1 and r2 and the resulting frequency response for the circuit of figure 29 . figure 16 shows the very clean and fast 10 v pulse response of the ad844. v in v out r3 optional r2 r1 ad844 r l c l 0 0897-029 figure 29. inverting amplifier
ad844 rev. f | page 13 of 20 table 3. gain vs. bandwidth gain r1 r2 bw (mhz) gbw (mhz) ?1 1 k 1 k 35 35 ?1 500 500 60 60 ?2 2 k 1 k 15 30 ?2 1 k 500 30 60 ?5 5 k 1 k 5.2 26 ?5 500 100 49 245 ?10 1 k 100 23 230 ?10 500 50 33 330 ?20 1 k 50 21 420 ?100 5 k 50 3.2 320 response as an i-v converter the ad844 works well as the active element in an operational current-to-voltage converter, used in conjunction with an exter- nal scaling resistor, r1, in figure 30 . this analysis includes the stray capacitance, c s , of the current source, which may be a high speed dac. using a conventional op amp, this capacitance forms a nuisance pole with r1 that destabilizes the closed-loop response of the system. most op amps are internally compensated for the fastest response at unity gain, so the pole due to r1 and c s reduces the already narrow phase margin of the system. for example, if r1 is 2.5 k, a c s of 15 pf places this pole at a fre- quency of about 4 mhz, well within the response range of even a medium speed operational amplifier. in a current feedback amp, this nuisance pole is no longer determined by r1 but by the input resistance, r in . because this is about 50 for the ad844, the same 15 pf forms a pole at 212 mhz and causes little trouble. it can be shown that the response of this system is: () () tn td sig out ss r1 k iv ++ = 11 where: k is a factor very close to unity and represents the finite dc gain of the amplifier. td is the dominant pole. tn is the nuisance pole. 1 rr r k t t + = td = kr 1c t tn = r in c s (assuming r in << r1 ) using typical values of r1 = 1 k and r t = 3 m, k = 0.9997; in other words, the gain error is only 0.03%. this is much less than the scaling error of virtually all dacs and can be absorbed, if necessary, by the trim needed in a precise system. in the ad844, r t is fairly stable with temperature and supply voltages, and consequently the effect of finite gain is negligible unless high value feedback resistors are used. because that results in slower response times than are possible, the relatively low value of r t in the ad844 is rarely a significant source of error. v out r1 ad844 r l c l i sig c s 0 0897-030 figure 30. current-to-voltage converter circuit description of the ad844 a simplified schematic is shown in figure 31 . the ad844 differs from a conventional op amp in that the signal inputs have radically different impedance. the noninverting input (pin 3) presents the usual high impedance. the voltage on this input is transferred to the inverting input (pin 2) with a low offset voltage, ensured by the close matching of like polarity transistors operating under essentially identical bias conditions. laser trimming nulls the residual offset voltage, down to a few tens of microvolts. the inverting input is the common emitter node of a complementary pair of grounded base stages and behaves as a current summing node. in an ideal current feedback op amp, the input resistance is zero. in the ad844, it is about 50 . a current applied to the inverting input is transferred to a complementary pair of unity-gain current mirrors that deliver the same current to an internal node (pin 5) at which the full output voltage is generated. the unity-gain complementary voltage follower then buffers this voltage and provides the load driving power. this buffer is designed to drive low impedance loads, such as terminated cables, and can deliver 50 ma into a 50 load while maintaining low distortion, even when operating at supply voltages of only 6 v. current limiting (not shown) ensures safe operation under short-circuited conditions. + in output 6 5 2 3 7 4 ?in +v s ?v s tz i b i b 0 0897-031 figure 31. simpli fied schematic
ad844 rev. f | page 14 of 20 noninverting gain of 100 it is important to understand that the low input impedance at the inverting input is locally generated and does not depend on feedback. this is very different from the virtual ground of a conventional operational amplifier used in the current summing mode, which is essentially an open circuit until the loop settles. in the ad844, transient current at the input does not cause voltage spikes at the summing node while the amplifier is settling. furthermore, all of the transient current is delivered to the slewing (tz) node (pin 5) via a short signal path (the grounded base stages and the wideband current mirrors). the ad844 provides very clean pulse response at high noninverting gains. figure 32 shows a typical configuration providing a gain of 100 with high input resistance. the feedback resistor is kept as low as practicable to maximize bandwidth, and a peaking capacitor (c pk ) can optionally be added to further extend the bandwidth. figure 33 shows the small signal response with c pk = 3 nf, r l = 500 , and supply voltages of either 5 v or 15 v. gain bandwidth products of up to 900 mhz can be achieved in this way. the current available to charge the capacitance (about 4.5 pf) at the tz node is always proportional to the input error current, and the slew rate limitations associated with the large signal response of the op amps do not occur. for this reason, the rise and fall times are almost independent of signal level. in practice, the input current eventually causes the mirrors to saturate. when using 15 v supplies, this occurs at about 10 ma (or 2200 v/s). because signal currents are rarely this large, classical slew rate limitations are absent. the offset voltage of the ad844 is laser trimmed to the 50 v level and exhibits very low drift. in practice, there is an additional offset term due to the bias current at the inverting input (i bn ), which flows in the feedback resistor (r1). this can optionally be nulled by the trimming potentiometer shown in figure 32 . offset trim c pk 3nf 20 ? 4.7 ? 0.22 f 0.22 f r l v in + v s ?v s ad844 r1 499 ? r2 4.99 ? 4.7 ? 1 2 3 8 7 4 6 00897-032 this inherent advantage is lost if the voltage follower used to buffer the output has slew rate limitations. the ad844 is designed to avoid this problem, and as a result, the output buffer exhibits a clean large signal transient response, free from anomalous effects arising from internal saturation. response as a noninverting amplifier because current feedback amplifiers are asymmetrical with regard to their two inputs, performance differs markedly in noninverting and inverting modes. in noninverting modes, the large signal high speed behavior of the ad844 deteriorates at low gains because the biasing circuitry for the input system (not shown in figure 31 ) is not designed to provide high input voltage slew rates. figure 32. noninverting amplifier gain = 100, optional offset trim is shown frequency (hz) gain (db) 46 16 100k 1m 20m 10m 40 34 28 22 00897-040 v s = 5v v s = 15v however, good results can be obtained with some care. the noninverting input does not tolerate a large transient input; it must be kept below 1 v for best results. consequently, this mode is better suited to high gain applications (greater than 10). figure 23 shows a noninverting amplifier with a gain of 10 and a bandwidth of 30 mhz. the transient response is shown in figure 26 and figure 27 . to increase the bandwidth at higher gains, a capacitor can be added across r2 whose value is approximately (r1/r2) c t . figure 33. ac response for gain = 100, configuration shown in figure 32
ad844 rev. f | page 15 of 20 using the ad844 board layout as with all high frequency circui ts considerable care must be used in the layout of the components surrounding the ad844. a ground plane, to which the power supply decoupling capaci- tors are connected by the shortest possible leads, is essential to achieving clean pulse response. even a continuous ground plane exhibits finite voltage drops between points on the plane, and this must be kept in mind when selecting the grounding points. in general, decoupling capacitors should be taken to a point close to the load (or output connector) because the load currents flow in these capacitors at high frequencies. the +in and ?in circuits (for example, a termination resistor and pin 3) must be taken to a common point on the ground plane close to the amplifier package. use low impedance 0.22 f capacitors (avx sr305c224kaa or equivalent) wherever ac coupling is required. include either ferrite beads and/or a small series resistance (approximately 4.7 ) in each supply line. input impedance at low frequencies, negative feedback keeps the resistance at the inverting input close to zero. as the frequency increases, the impedance looking into this input increases from near zero to the open-loop input resistance, due to bandwidth limitations, making the input seem inductive. if it is desired to keep the input impedance flatter, a series rc network can be inserted across the input. the resistor is chosen so that the parallel sum of it and r2 equals the desired termination resistance. the capacit- ance is set so that the pole determined by this rc network is about half the bandwidth of the op amp. this network is not important if the input resistor is much larger than the termination used, or if frequencies are relatively low. in some cases, the small peaking that occurs without the network can be of use in extending the ?3 db bandwidth. driving large capacitive loads capacitive drive capability is 100 pf without an external net- work. with the addition of the network shown in figure 34 , the capacitive drive can be extended to over 10,000 pf, limited by internal power dissipation. with capacitive loads, the output speed becomes a function of the overdriven output current limit. because this is roughly 100 ma, under these conditions, the maximum slew rate into a 1000 pf load is 100 v/s. figure 35 shows the transient response of an inverting amplifier (r1 = r2 = 1 k) using the feedforward network shown in figure 34 , driving a load of 1000 pf. ad844 v out c l 750 ? 22pf 6 5 00897-034 figure 34. feedforward network for large capacitive loads 00897-035 5v 10 500ns 100 0 90 figure 35. driving 1000 pf c l with feedforward network of figure 34 settling time settling time is measured with the circuit of figure 36 . this circuit employs a false summing node, clamped by the two schottky diodes, to create the error signal and limit the input signal to the oscilloscope. for measuring settling time, the ratio of r6/r5 is equal to r1/r2. for unity gain, r6 = r5 = 1 k, and r l = 500 . for the gain of ?10, r5 = 50 , r6 = 500 , and r l was not used because the summing network loads the output with approximately 275 . using this network in a unity-gain configuration, settling time is 100 ns to 0.1% for a C5 v to +5 v step with c l = 10 pf. r5 d1 d2 r1 r2 r3 r l r6 v in c l v out to scope (tek 7a11 fet probe) notes 1. d1, d2 in6263 or equivalent schottky diode. ad844 00897-036 figure 36. settling time test fixture
ad844 rev. f | page 16 of 20 dc error calculation figure 37 shows a model of the dc error and noise sources for the ad844. the inverting input bias current, i bn , flows in the feedback resistor. i bp , the noninverting input bias current, flows in the resistance at pin 3 (r p ), and the resulting voltage (plus any offset voltage) appears at the inverting input. the total error, v o , at the output is: () r1i r2 r1 rivriv bn inbn os pbp o + ? ? ? ? ? ? + ++= 1 because i bn and i bp are unrelated both in sign and magnitude, inserting a resistor in series with the noninverting input does not necessarily reduce dc error and may actually increase it. r2 v n i nn i np r p r1 i bp i bn v os ad844 r in 00897-037 figure 37. offset voltage and noise model for the ad844 noise noise sources can be modeled in a manner similar to the dc bias currents, but the noise sources are i nn , i np , v n , and the amplifier induced noise at the output, v on , is: () () () 2 2 2 2 1 r1i r2 r1 vriv nn n pnp on + ? ? ? ? ? ? ++ = overall noise can be reduced by keeping all resistor values to a minimum. with typical numbers, r1 = r2 = 1 k, r p = 0 , v n = 2 nv/hz, i np = 10 pa/hz, i nn = 12 pa/hz, and v on calculates to 12 nv/hz. the current noise is dominant in this case, because it is in most low gain applications. video cable driver using 5 v supplies the ad844 can be used to drive low impedance cables. using 5 v supplies, a 100 load can be driven to 2.5 v with low distortion. figure 38 shows an illustrative application that provides a noninverting gain of +2, allowing the cable to be reverse-terminated while delivering an overall gain of +1 to the load. the ?3 db bandwidth of this circuit is typically 30 mhz. figure 39 shows a differential gain and phase test setup. in video applications, differential-phase and differential-gain characteris- tics are often important. figure 40 shows the variation in phase as the load voltage varies. figure 41 shows the gain variation. v in 50 ? 50 ? r l 50 ? 300 ? 300 ? 3 2 +5 v ?5v 7 6 4 2.2f 2.2f z o = 50 ? v out 0 0897-038 figure 38. the ad844 as a cable driver hp8753a network analyzer hp11850c splitter circuit under test hp3314a staircase generator v out v in v in out out out in rf out rf in ext trig sync out 50? (terminator) out 470 ? 0 0897-039 figure 39. differential gain/phase test setup v out (ire) differential phase (degrees) 0.3 0.2 ?0.3 90 18 0 36 54 72 0.1 0 ?0.1 ?0.2 ire = 7.14mv 00897-040 figure 40. differential phase for the circuit of figure 38 v out (ire) differential gain (%) 0.06 0.04 ?0.06 01 8 9 36 54 72 0.02 0 ?0.02 ?0.04 0 ire = 7.14mv 00897-041 figure 41. differential gain for the circuit of figure 38
ad844 rev. f | page 17 of 20 top view (not to scale) 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 ad568 +15v (v cc ) refcom ?15v (v ee ) i bpo i out r l acom lcom span span thcom v th digital inputs +15v ?15v v out analog supply ground digital supply ground ?5v 100pf 0.22f* 0.22f* 0.22f* 0.22f* *power supply bypass capacitors. r i ad844 msb lsb 6 7 4 3 2 0 0897-042 figure 42. high speed dac amplifier high speed dac buffer the ad844 performs very well in applications requiring current- to-voltage conversion. figure 42 shows connections for use with the ad568 current output dac. in this application, the bipolar offset is used so that the full-scale current is 5.12 ma, which generates an output of 5.12 v using the 1 k application resistor on the ad568. figure 43 shows the full-scale transient response. care is needed in power supply decoupling and grounding techniques to achieve the full 12-bit accuracy and realize the fast settling capabilities of the system. the ad568 data sheet should be consulted for more complete details about its use. 0 0897-043 2v 10 50ns 100 0 90 figure 43. dac amplifier full-scale transient response 20 mhz variable gain amplifier the ad844 is an excellent choice as an output amplifier for the ad539 multiplier, in all of its connection modes. (see the ad539 data sheet for full details.) figure 44 shows a simple multiplier providing the output: v vv v yx w 2 ?= (1) where v x is the gain control input, a positive voltage from 0 v to 3.2 v (maximum), and v y is the signal voltage, nominally 2 v full scale but capable of operation up to 4.2 v. the peak output in this configuration is thus 6.7 v. using all four of the internal application resistors provided on the ad539 in parallel results in a feedback resistance of 1.5 k, at which value the bandwidth of the ad844 is about 22 mhz, and is essentially independent of v x . the gain at v x = 3.16 v is 4 db. inputs v y * 2v fs 3nf input gnd 0.22f 0.22f 0.22f 1 2 3 4 5 6 7 ad539 top view (not to scale) 8 0.22f + v s typ +6v at 15a ?v s typ ?6v at 15a 10 ? 10 ? 10 ? 10 ? v w = 2v ?v x v y output v w *v x and v y inputs may optionally be terminated; typically by using a 50 ? or 75 ? resistor to ground. v x * 0v to 3 v 2 3 7 6 4 ad844 9 16 15 14 13 12 11 10 00897-044 figure 44. 20 mhz vga using the ad539
ad844 rev. f | page 18 of 20 figure 45 shows the small signal response for a 50 db gain control range (v x = 10 mv to 3.16 v). at small values of v x , capacitive feedthrough on the pc board becomes troublesome and very careful layout techniques are needed to minimize this problem. a ground strip between the pins of the ad539 is helpful in this regard. figure 46 shows the response to a 2 v pulse on v y for v x = 1 v, 2 v, and 3 v. for these results, a load resistor of 500 was used and the supplies were 9 v. the multiplier operates from supplies between 4.5 v and 16.5 v. disconnecting pin 9 and pin 16 on the ad539 alters the denominator in equation 1 to 1 v, and the bandwidth is approximately 10 mhz, with a maximum gain of 10 db. using only pin 9 or pin 16 results in a denominator of 0.5 v, a bandwidth of 5 mhz, and a maximum gain of 16 db. frequency (hz) gain (db) 4 ?6 ?56 60m 1m 100k 10m ?26 ?36 ?46 ?16 v x = 3.15v v x = 1.0v v x = 0.316v v x = 0.10v v x = 0.032v 00897-045 figure 45. vga ac response 00897-046 1v 1v 50ns 10 100 0 90 figure 46. vga transient response with v x = 1 v, 2 v, and 3 v
ad844 rev. f | page 19 of 20 outline dimensions compliant to jedec standards ms-001 controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. corner leads may be configured as whole or half leads. 070606-a 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) seating plane 0.015 (0.38) min 0.210 (5.33) max 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) 8 1 4 5 0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 0.100 (2.54) bsc 0.400 (10.16) 0.365 (9.27) 0.355 (9.02) 0.060 (1.52) max 0.430 (10.92) max 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.195 (4.95) 0.130 (3.30) 0.115 (2.92) 0.015 (0.38) gauge plane 0.005 (0.13) min figure 47. 8-lead plastic dual-in-line package [pdip] (n-8) dimensions shown in inches and (millimeters) controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. 0.310 (7.87) 0.220 (5.59) 0.005 (0.13) min 0.055 (1.40) max 0.100 (2.54) bsc 15 0 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20) seating plane 0.200 (5.08) max 0.405 (10.29) max 0.150 (3.81) min 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.070 (1.78) 0.030 (0.76) 0.060 (1.52) 0.015 (0.38) 14 5 8 figure 48. 8-lead ceramic dual in-line package [cerdip] (q-8) dimensions shown in inches and (millimeters)
ad844 rev. f | page 20 of 20 controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-013- aa 032707-b 10.50 (0.4134) 10.10 (0.3976) 0.30 (0.0118) 0.10 (0.0039) 2.65 (0.1043) 2.35 (0.0925) 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) 0 . 7 5 ( 0 . 0 2 9 5 ) 0 . 2 5 ( 0 . 0 0 9 8 ) 45 1.27 (0.0500) 0.40 (0.0157) c oplanarity 0.10 0.33 (0.0130) 0.20 (0.0079) 0.51 (0.0201) 0.31 (0.0122) seating plane 8 0 16 9 8 1 1.27 (0.0500) bsc figure 49. 16-lead standard small outline package [soic_w] wide body (rw-16) dimensions shown in millimeters and (inches) ordering guide model temperature range packag e description package option ad844an ?40c to +85c 8-lead plastic dual in-line package [pdip] n-8 ad844anz 1 ?40c to +85c 8-lead plastic dual in-line package [pdip] n-8 ad844achips ?40c to +85c die ad844aq ?40c to +85c 8-lead ceramic dual in-line package [cerdip] q-8 ad844bq ?40c to +85c 8-lead ceramic dual in-line package [cerdip] q-8 ad844jr-16 0c to 70c 16-lead standard small outline package [soic_w] rw-16 ad844jr-16-reel 0c to 70c 16-lead soic_w, 13 tape and reel rw-16 ad844jr-16-reel7 0c to 70c 16-lead soic_w, 7 tape and reel rw-16 ad844jrz-16 1 0c to 70c 16-lead standard small outline package [soic_w] rw-16 ad844jrz-16-reel 1 0c to 70c 16-lead soic_w, 13 tape and reel rw-16 ad844jrz-16-reel7 1 0c to 70c 16-lead soic_w, 7 tape and reel rw-16 ad844schips ?55c to +125c die ad844sq ?55c to +125c 8-lead ceramic dual in-line package [cerdip] q-8 ad844sq/883b ?55c to +125c 8-lead ceramic dual in-line package [cerdip] q-8 5962-8964401pa 2 ?55c to +125c 8-lead ceramic dual in-line package [cerdip] q-8 1 z = rohs compliant part. 2 refer to the desc drawing for tested specifications. ?1989C2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d00897-0-2/09(f)

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